The present invention relates generally to controlling system clocks and specifically to controlling system clock rate in response to an environmental condition.
Through increasingly larger die sizes and circuit miniaturization techniques, advances in integrated circuit (IC) fabrication have lead to the development of individual ICs housing millions of transistors. At the same time, these densely populated ICs are performing greater and greater numbers of operations per second. As a result, today""s microprocessors operate at higher power levels producing heat that must be managed to prevent failures. External cooling devices can be used to dissipate heat. These devices include both passive devices, such as heat sinks, and active devices such as fans and thermoelectric coolers. More recent techniques include the incorporation of thermal sensors within ICs that monitor on-die temperature and provide control signals to an active cooling system. Other solutions include an ability to control IC temperature without the use of external cooling mechanisms. One solution incorporates a clock-throttling mechanism used to slow the processing speed of the IC in response to an over-temperature condition reported by the IC""s thermal sensor. The reduction in processing speed reduces power consumption thereby reducing the amount of heat to be dissipated.
Fault-tolerant computing systems that use hardware redundancy may be constructed with multiple modules, such as central processing units (CPUs), operating in a synchronous, lock-step relationship (performing the same instructions on the same clock cycle). It is desirable for these systems to employ current-technology, enabling commodity ICs to reap the benefits of reduced size, increased performance and reduced cost. Being subject to the thermal conditions described above, it is desirable to utilize ICs with a thermal sensing capability in combination with a clock- throttling technique to manage the thermal load while preserving system reliability. However, allowing each processor within a fault-tolerant system to reduce its own clock rate as its temperature rose above a predetermined threshold would remove the ability of the processors to operate in lock step. This is because thermal gradients caused by ambient conditions would result in the on-die temperature of individual processors increasing above a common threshold at different times. This loss of synchronization would then result in system failures. The present invention avoids this problem.
The present invention relates to methods and apparatus for controlling central processing unit (CPU) power consumption in response to a reported environmental condition by varying the clock rate of each processor of a synchronous multi-processor system. The object of this invention is to maintain synchronization of all processors before, during, and after any clock-rate variation response to reported environmental conditions.
In accordance with one embodiment of the invention, a computer system employs two or more identical CPUs, each containing a microprocessor executing the same instructions at substantially the same time, according to the processor clock rate. Each microprocessor includes a thermal sensor that continuously monitors the on-die temperature and compares it to a pre-stored threshold value. In this embodiment, one feature of the invention is that when the measured on-die processor temperature crosses the threshold value, the microprocessor writes the result to a common, external interrupt register.
Another feature of the invention is the simultaneous interrupt notification to all CPUs of the multi-processor system of a reported over-temperature condition on any CPU. Upon interrupt notification, each microprocessor halts all applications and enters a service-handling routine where the contents of the interrupt register are read to determine the cause of the interrupt. Yet another feature of the invention is the simultaneous reduction of each processor clock rate to a lower rate in response to the reported over-temperature interrupt. In one embodiment, the microprocessor controls a local phase-locked loop (PLL) to reduce its local clock rate. When the microprocessor detects an over-temperature condition, it actuates a reduction of the local clock rate to a lower rate. Operation at the lower clock rate will reduce microprocessor power consumption resulting in an eventual reduction of the microprocessor""s, on-die temperature.
In another embodiment, one feature of the invention is a software-controlled polling of each CPU to report any over-temperature conditions. In this embodiment, each microprocessor is in communication with a register having a bit, or multiple bits, that effects control of the processor clock rate. Other embodiments are envisioned where the register effecting control of the processor clock rate may be contained within the microprocessor. Another feature of the invention is to simultaneously set the clock rate reduction bit, or multiple bits, within each register.